NAND ARRAY HIARCHICAL BL STRUCTURES FOR MULTIPLE-WL AND ALL -BL SIMULTANEOUS ERASE, ERASE-VERIFY, PROGRAM, PROGRAM-VERIFY, AND READ OPERATIONS

摘要

Several 2D and 3D HiNAND flash memory arrays with 1 -level or 2-level broken BL- hierarchical structures are provided for Multiple Whole- WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple l(top)-level broken metal2 GBLs plus optional lower-level broken metal 1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metalO power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple- WL and All-BL Program and Program- Verify operation with reduced program current for highest program yield superior P/E cycles.