METHOD FOR DESIGNING ANTENNA CELL THAT PREVENTS PLASMA INDUCED GATE DIELECTRIC DAMAGE IN SEMICONDUCTOR INTEGRATED CIRCUITS

摘要

An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

主权项

1. A method for forming a semiconductor structure, said method comprising:
providing a semiconductor substrate; defining an antenna cell on a surface of said semiconductor substrate; forming a plurality of substantially parallel polysilicon lines having substantially the same length and extending completely through said cell; forming a dummy transistor using one said polysilicon line as a dummy gate thereof, said dummy transistor including said dummy gate disposed over a gate dielectric disposed over a continuous source/drain dopant impurity region; and forming a metal lead coupled to an active transistor gate and further coupled to a diode formed of said dummy transistor, wherein said dummy gate is coupled to said semiconductor substrate and said metal lead is coupled to said continuous source/drain dopant impurity region.