| 发明名称 |
Semiconductor memory device |
| 摘要 |
A semiconductor memory device including a memory cell array including at least one word line, at least one cell bit line, and at least one memory cell that is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier that is disposed above or below the memory cell array to be overlapped with the memory cell array in a planar fashion, connected to at least one bit line connected to the at least one cell bit line, and at least one complementary bit line corresponding to the at least one bit line, and senses data stored in the at least one memory cell; a decompression unit for decompressing a signal having a lower voltage level from among a signal of the at least one bit line and a signal of the at least one complementary bit line; a boosting unit for boosting a signal having a higher voltage level from among the signal of the at least one bit line and the signal of the at least one complementary bit line; and an equalizing unit for equalizing the signal of the at least one bit line and the signal of the at least one complementary bit line. |
| 申请公布号 |
US8958257(B2) |
申请公布日期 |
2015.02.17 |
| 申请号 |
US201113808252 |
申请日期 |
2011.01.07 |
| 申请人 |
|
发明人 |
Yoon Jae Man |
| 分类号 |
G11C7/02;G11C7/06;G11C5/06;G11C5/02;G11C11/4094;G11C11/4097;G11C11/4074 |
主分类号 |
G11C7/02 |
| 代理机构 |
Nixon Peabody LLP |
代理人 |
Nixon Peabody LLP |
| 主权项 |
1. A semiconductor memory device comprising:
a memory cell array that is disposed at a first layer and comprises at least one word line, at least one cell bit line, and at least one memory cell which is disposed in a region where the at least one word line and the at least one cell bit line cross each other; at least one sense amplifier configured to sense data stored in the at least one memory cell, the at least one sense amplifier being disposed at a second layer different from the first layer and connected to at least one bit line and at least one complementary bit line, the at least one bit line being connected to the at least one cell bit line, at least one output device that is connected to the at least one cell bit line, wherein the bit line is connected to the output device via the cell bit line, wherein the memory cell array is overlapped with the at least one sense amplifier in a planar fashion, the at least one output device is connected to the at least one sense amplifier so as not to be overlapped with the memory cell array and the at least one sense amplifier in a planar fashion, and the at least one output device transmits a signal of the at least one bit line to an output line. |
| 地址 |
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