Apparatuses and methods for improved memory operation times

摘要

Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the first and second lines. The sense amplifier may sense a differential signal between the first and second lines and amplify the same. An example method may include accessing a first memory cell coupled to a first line of a pair of lines and accessing a second memory cell coupled to a second line of the pair of lines. A differential is sensed between the pair of lines with a sense amplifier coupled directly to the pair of lines, and the sensed differential is amplified. The sense amplifier is coupled to an input/output bus to provide the amplified sensed differential to the input/output bus.

主权项

1. An apparatus, comprising:
an input/output bus; first and second lines; and a sense amplifier directly coupled to the first and second lines, the sense amplifier configured to sense a differential signal between the first and second lines and amplify the same, wherein the sense amplifier is further configured to be selectively coupled to the input/output bus based, at least in part, on a column select signal and wherein the sense amplifier is further configured to provide the differential signal to the input/output bus.