发明名称 |
Signal processing circuit |
摘要 |
To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off. |
申请公布号 |
US8958252(B2) |
申请公布日期 |
2015.02.17 |
申请号 |
US201414272598 |
申请日期 |
2014.05.08 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Kobayashi Hidetomo;Maehashi Yukio |
分类号 |
G11C7/10;G11C11/4074;G11C11/407 |
主分类号 |
G11C7/10 |
代理机构 |
Fish & Richardson P.C. |
代理人 |
Fish & Richardson P.C. |
主权项 |
1. A signal processing circuit comprising:
an arithmetic portion; a memory; and a control portion configured to control the arithmetic portion and the memory, wherein the control portion includes a first memory circuit and a second memory circuit for storing data held in the first memory circuit, wherein the second memory circuit includes a first transistor and a first capacitor, wherein a first electrode of the first capacitor is electrically connected to a first node which is set in a floating state when the first transistor is turned off, wherein the memory includes a plurality of third memory circuits arranged in matrix, wherein the plurality of third memory circuits each includes a second transistor and a second capacitor, wherein a first electrode of the second capacitor is electrically connected to a second node which is set in a floating state when the second transistor is turned off, and wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer. |
地址 |
Atsugi-shi, Kanagawa-ken JP |