Methods and apparatus for reusing snoop responses and data phase results in a cache controller

摘要

Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache controllers; receives broadcast cache line data from a source cache as instructed by the bus controller for the entry during a data phase; and processes a subsequent cache transaction CTR2 for the entry based on one or more of the broadcast combined snoop response and the broadcast cache line data.

主权项

1. A method, comprising:
receiving a broadcast combined snoop response and at least one sideband signal from a bus controller, wherein said broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein said combined snoop response is a combination of at least one snoop response from a plurality of cache controllers, wherein said bus controller broadcasts said broadcast combined snoop response to a plurality of cache controllers, wherein said at least one sideband signal indicates one or more of a status and a phase of bus transaction merging performed by said bus controller; receiving broadcast cache line data from a source cache as instructed by said bus controller for said entry during a data phase, wherein said source cache broadcasts said broadcast cache line data to a plurality of peer cache controllers with at least one additional sideband signal; and processing a subsequent cache transaction CTR2 for said entry based on one or more of said broadcast combined snoop response and said broadcast cache line data by using at least one of said sideband signals to align with merged bus transaction phases of said incoming bus transaction BTR1 and said subsequent cache transaction CTR2 to implement said bus transaction merging.