发明名称 |
Imaging apparatus and imaging system |
摘要 |
Because a conventionally known imaging apparatus includes a buffer element for each signal processing circuit, the number of buffer elements increases in proportion to the number of signal processing circuits. The delayed supply of a drive signal within a group of a plurality of signal processing circuits may require the operation timing margin to be set longer. In other words, the operational speed is hard to increase. First buffer circuits connected in series and second buffer circuits connected in parallel with the first buffer circuits are provided, and one second buffer circuit supplies a drive signal to a plurality of signal processing units. |
申请公布号 |
US8964080(B2) |
申请公布日期 |
2015.02.24 |
申请号 |
US201213490784 |
申请日期 |
2012.06.07 |
申请人 |
Canon Kabushiki Kaisha |
发明人 |
Kobayashi Daisuke;Yamazaki Yoshikazu |
分类号 |
H04N5/335;H04N5/374 |
主分类号 |
H04N5/335 |
代理机构 |
Canon U.S.A. Inc., IP Division |
代理人 |
Canon U.S.A. Inc., IP Division |
主权项 |
1. An imaging apparatus comprising: a pixel array; a first signal processing group and a second signal processing group each of which includes a plurality of signal processing units each of which is provided correspondingly to a column of the pixel array; and a drive signal transmitting unit which transmits a drive signal that drives the signal processing units, and which includes a plurality of first buffer circuits and a plurality of second buffer circuits,
wherein an output terminal of one of the plurality of second buffer circuits is connected to the first signal processing group not via any other buffer circuit, and an output terminal of another one of the second buffer circuits is connected to the second signal processing group not via any other buffer circuit, and wherein an output terminal of one of the plurality of first buffer circuits is connected to an input terminal of the one of the plurality of second buffer circuits and an input terminal of another one of the plurality of first buffer circuits, and an output terminal of the another one of the plurality of first buffer circuits is connected to an input terminal of the another one of the plurality of second buffer circuits. |
地址 |
Tokyo JP |