Multi-phase clock signal generation circuits

摘要

Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.

主权项

1. A multi-phase clock signal generation circuit, comprising:
first transistor and second transistor of a first channel type; third transistor and fourth transistor of a second channel type, wherein sources of the first transistor and second transistor are grounded, a drain of the first transistor is coupled to a source of the third transistor and a gate of the fourth transistor, a drain of the second transistor is coupled to a source of the fourth transistor and a gate of the third transistor, and drains of the third transistor and the fourth transistor are coupled to a power supply; a first delay unit having an input for receiving a clock signal and an output coupled to a gate of the first transistor; a second delay unit having an input for receiving an inverted clock signal of the clock signal and an output coupled to a gate of the second transistor; wherein a first clock signal is outputted at a node between the drain of the second transistor and the source of the fourth transistor, and a third clock signal is outputted at a node between the drain of the first transistor and the source of the third transistor.