| 发明名称 | High electron mobility transistor | ||
| 摘要 | A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode. | ||
| 申请公布号 | US8963162(B2) | 申请公布日期 | 2015.02.24 |
| 申请号 | US201113339052 | 申请日期 | 2011.12.28 |
| 申请人 | Taiwan Semiconductor Manufacturing Company, Ltd. | 发明人 | Hsu Chun-Wei;Yu Jiun-Lei Jerry;Yao Fu-Wei;Yu Chen-Ju;Chen Po-Chih;Wong King-Yuen |
| 分类号 | H01L29/778 | 主分类号 | H01L29/778 |
| 代理机构 | Lowe Hauptman & Ham, LLP | 代理人 | Lowe Hauptman & Ham, LLP |
| 主权项 | 1. A high electron mobility transistor (HEMT) comprising: a first III-V compound layer; a second III-V compound layer disposed on the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located between the first III-V compound layer and the second III-V compound layer; a source feature and a drain feature disposed on the second III-V compound layer, each of the source feature and the drain feature comprising a corresponding intermetallic compound at least partially embedded in the second III-V compound layer, wherein each intermetallic compound is free of Au and comprises Al, Ti or Cu, wherein each intermetallic compound has a non-flat top surface; one or more isolation regions embedded in the first III-V compound layer and the second III-V compound layer; a p-type layer overlying each of a portion of a dielectric cap layer, a portion of a protection layer, and a portion of the second III-V compound layer between the source feature and the drain feature; a gate electrode disposed on the p-type layer; and a depletion region disposed in the carrier channel and under the gate electrode. | ||
| 地址 | TW | ||