MULTI-CORE SYNCHRONIZATION MECHANISM

摘要

A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

主权项

1. A microprocessor, comprising:
a control unit, configured to selectively control a respective clock signal to each of a plurality of processing cores; the plurality of processing cores, each configured to separately write a value to the control unit; wherein, for each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit; wherein the control unit is configured to detect a condition has occurred when all of the plurality of processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the plurality of processing cores; and wherein the control unit is configured to simultaneously turn on the respective clock signal to all of the plurality of processing cores in response to detecting the condition has occurred.