METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING LAYOUT FOR SEMICONDUCTOR DEVICE

摘要

A method is performed at least in part by at least one processor. In the method, a plurality of circuit elements are placed in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins. A layer assignment is generated to assign a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins. The plurality of interconnections is routed in the layout in accordance with the layer assignment.

主权项

1. A method performed at least in part by at least one processor, the method comprising:
placing a plurality of circuit elements, by the at least one processor, in a layout for a semiconductor device, the plurality of circuit elements having a plurality of pins; generating a layer assignment which assigns a plurality of interconnections to corresponding conductive layers of the semiconductor device, the plurality of interconnections connecting corresponding pairs of pins among the plurality of pins, wherein the plurality of interconnections is not yet routed in the layout during the generation of the layer assignment; and routing, after generating the layer assignment, the plurality of interconnections in the layout in accordance with the layer assignment.