FORMING SILICIDE AND CONTACT AT EMBEDDED EPITAXIAL FACET

摘要

In described examples, an integrated circuit (100) is formed with an MOS transistor (108) abutting field oxide (106) and a gate structure (110) on the field oxide (106) adjacent to the MOS transistor (108). A gap (146) between an epitaxial source/drain (124) and the field oxide (106) is formed with a silicon dioxide-based gap filler (148) in the gap (146). Metal silicide (150) is formed on the exposed epitaxial source/drain region (124). A CESL (152) is formed over the integrated circuit (100), and a PMD layer (154) is formed over the CESL (152). A contact (156) is formed through the PMD layer (154) and CESL (152) to make an electrical connection to the metal silicide (150) on the epitaxial source/drain region (124).