发明名称 APPARATUS AND METHODS FOR FREQUENCY LOCK ENHANCEMENT OF PHASE-LOCKED LOOPS
摘要 Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.
申请公布号 US2015180485(A1) 申请公布日期 2015.06.25
申请号 US201314134767 申请日期 2013.12.19
申请人 Analog Devices Technology 发明人 Shanan Hyman;Keaveney Michael F.
分类号 H03L7/099;H03L7/093 主分类号 H03L7/099
代理机构 代理人
主权项 1. A phase-locked loop (PLL) comprising: a voltage controlled oscillator (VCO) having a tuning voltage input, wherein an oscillation frequency of the VCO changes in relation to the voltage level of the tuning voltage input, wherein the VCO is configured to generate an oscillation signal that oscillates at the oscillation frequency; and a frequency tuning circuit configured to set a frequency band setting of the VCO, the frequency tuning circuit comprising: a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels;a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO; andan amplitude detection circuit configured to compare an amplitude of the oscillation signal to one or more amplitude threshold levels.
地址 Hamilton BM
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