发明名称 Wiring Substrate and Semiconductor Device
摘要 A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.
申请公布号 US2015179560(A1) 申请公布日期 2015.06.25
申请号 US201414548784 申请日期 2014.11.20
申请人 SHINKO ELECTRIC INDUSTRIES CO., LTD. 发明人 Arisaka Hiromu;SHIMIZU Noriyoshi;TANAKA Masato;KOYAMA Tetsuya;ROKUGAWA Akio
分类号 H01L23/498;H05K1/03;H05K1/11;H05K1/02;H01L25/10;H01L23/31 主分类号 H01L23/498
代理机构 代理人
主权项 1. A wiring substrate comprising: a first wiring structure that includes a core substrate,a first insulation layer stacked on an upper surface of the core substrate and formed from a thermosetting insulative resin including a first reinforcement material,a second insulation layer stacked on a lower surface of the core substrate and formed from a thermosetting insulative resin including a second reinforcement material, anda via wire formed in the first insulation layer; a second wiring structure that includes a plurality of third insulation layers, of which the main component is a photosensitive resin, formed on an upper surface of the first insulation layer, anda plurality of first wiring layers alternately formed in the plurality of third insulation layers at the upper surface of the first insulation layer, wherein the plurality of first wiring layers include a lowermost first wiring layer formed on the upper surface of the first insulation layer and an upper end surface of the via wire, andan uppermost first wiring layer including a pad used to electrically connect a semiconductor chip and the lowermost first wiring layer; a second wiring layer stacked on a lower surface of the second insulation layer; and an outermost insulation layer, of which the main component is a photosensitive resin, stacked on the lower surface of the second insulation layer to cover the second wiring layer, wherein the outermost insulation layer includes an opening that exposes a portion of the second wiring layer as an external connection pad, andthe second wiring structure has a higher wiring density than the first wiring structure.
地址 Nagano-ken JP