Invalid signal filtering method and shifter utilizing the method

摘要

A shifter with invalid signal filtering mechanism, comprising: a first shifting stage, for receiving and capturing an input signal in a first clock cycle; and a second shifting stage, after the first shifting stage, for receiving the input signal from the first shifting stage, and for receiving a validity signal indicating whether the input signal is valid or invalid, before a second clock cycle next to the first clock cycle occurs; wherein the second shifting stage captures the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is valid, where the second shifting stage does not capture the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is invalid.

主权项

1. An invalid signal filtering method, applied to a shifter including a first shifting stage and a second shifting stage after the first shifting stage, the invalid signal filtering method comprising:
utilizing the first shifting stage to receive and to capture an input signal in a first clock cycle; determining if the input signal is valid or invalid, before a second clock cycle next to the first clock cycle occurs; and utilizing the second shifting stage to capture the input signal transmitted from the first shifting stage if the input signal is determined to be valid, and not utilizing the second shifting stage to capture the input signal transmitted from the first shifting stage if the input signal is determined to be invalid; wherein the input signal is an unfiltered read command signal.