发明名称 Apparatus and methods for amplifier fault protection
摘要 An amplifier includes a fault protection control circuit biased from the signal pin and a fault protection circuit including a first PMOS transistor and a second PMOS transistor. The sources and bodies of the first and second PMOS transistors can be connected to one another, the drain of the first PMOS transistor can be connected to the amplifier's output, and the drain of the second PMOS transistor can be connected to a signal pin. During normal operating conditions, the fault protection control circuit can turn on the first and second PMOS transistors. However, the fault protection control circuit can turn off the first PMOS transistor and turn on the second PMOS transistor when an overvoltage condition is detected, and can turn on the first PMOS transistor and turn off the second PMOS transistor when an undervoltage condition is detected, even when the integrated circuit is unpowered.
申请公布号 US9088256(B2) 申请公布日期 2015.07.21
申请号 US201213570101 申请日期 2012.08.08
申请人 Analog Devices, Inc. 发明人 Cosgrave Gavin P.;Salcedo Javier Alejandro;Huang Yuhong;Clarke David J.;Li Minsheng
分类号 H02H3/20;H03F1/52;H03G11/08;H03G1/00;G01R17/02;G01R1/30;G01R19/00;H02H3/24 主分类号 H02H3/20
代理机构 Knobbe Martens Olson & Bear LLP 代理人 Knobbe Martens Olson & Bear LLP
主权项 1. An apparatus comprising: an amplifier including an output configured to generate an output signal; a signal pin configured to receive the output signal from the output of the amplifier; a fault protection circuit electrically connected between the output of the amplifier and the signal pin, wherein the fault protection circuit comprises a first transistor and a second transistor, wherein the first transistor includes a drain electrically connected to the output of the amplifier, a source, and a gate, and wherein the second transistor includes a drain electrically connected to the signal pin, a source electrically connected to the source of the first transistor, and a gate; and a fault protection control circuit configured to control the fault protection circuit at least in part by controlling voltage levels of the gates of the first and second transistors, wherein the fault protection control circuit includes an overvoltage detection and control circuit configured to detect an overvoltage condition of the signal pin and to turn off the first transistor when the overvoltage condition is detected and otherwise turn on the first transistor, and wherein the fault protection circuit further includes an undervoltage detection and control circuit configured to detect an undervoltage condition of the signal pin and to turn off the second transistor when the undervoltage condition is detected and otherwise turn on the second transistor, wherein the overvoltage detection and control circuit is powered at least in part by the signal pin, wherein the undervoltage detection and control circuit is configured to turn on the second transistor during the overvoltage condition.
地址 Norwood MA US