Scan chain latch design that improves testability of integrated circuits

摘要

A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

主权项

1. A scan chain latch circuit comprising:
a first latch for holding one data value; a second latch for holding another data value; a multiplexor including first and second data inputs, a select input, and an output, wherein the one data value is applied to the first data input and said another data value is applied to the second data input; and a clock sub circuit for applying an alternating clock signal to the select input of the multiplexor to control a value on the output of the multiplexor, wherein the value on the output of the multiplexor toggles between said one data value and said another data value at a defined frequency.