| 摘要 |
PROBLEM TO BE SOLVED: To provide a circuit for adjusting timing among clock signals having different frequencies.SOLUTION: A timing adjustment circuit includes: a detector which generates a detection signal showing timing relation among a first clock signal with a duty ratio of 50% having a first frequency, a second clock signal with the duty ratio of 50% having a second frequency which is 1/2 of the first frequency, and a third clock signal with the duty ratio of 50% whose phase is shifted with that of the second clock signal by 90 degrees according to the first clock signal, the second clock signal, and the third clock signal; a low-pass filter which uses the detection signal to be generated by the detector as input; and a variable delay circuit which adjusts relative timing relation between the first clock signal and the second clock signal so that a center position of pulses of the first clock signal coincides with a center position of pulses of the second clock signal according to output of the low-pass filter. |
