Protection Scheme for Embedded Code

摘要

A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

主权项

1. An integrated circuit comprising a memory and a processor, the memory comprising one or more memory regions and the processor comprising:
an instruction pipeline comprised of a plurality of processing stages; a first processing stage, of the plurality of processing stages, having a first input coupled to receive one or more instructions; and a second processing stage, of the plurality of processing stages, coupled to first processing stage and configured to:
receive address information identifying a protected memory region of the memory, the protected memory region associated with an instruction received from the first processing stage;receive protection information for an identified protected memory region, wherein the protection information indicates a protection state assigned to the identified protected memory region; andcontrol access to the one or more memory regions based at least in part on the protection information for the identified protected memory region and an instruction type of the received instruction.