| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of increasing a DAC bit number without increasing the counter clock frequency for DAC and with a configuration with cost increase suppressed. <P>SOLUTION: A comparator 161 outputs a coincidence pulse when a counter value and a pixel value of digital image data coincide with each other. A 4-input 1-output D/S 162 selects one comparator clock from four comparator clocks CP1-CP4 the phases of which are different from each other by 90 degree on the basis of the value of the two least significant bit data of the digital image data. A DFF 163 latches the coincidence pulse at a rising edge timing of the selected comparator clock and outputs a low level gate signal VSW_GATE to an analog SW 164 to control the switch to be turned off. With this, a ramp signal is sampled. The sampling level of the ramp signal is equivalent to the voltage of the analog signal obtained by DA-converting the digital image data. <P>COPYRIGHT: (C)2013,JPO&INPIT</p> |
