发明名称 Control of warpage using ABF GC cavity for embedded DIE package
摘要 Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material.
申请公布号 GB201514666(D0) 申请公布日期 2015.09.30
申请号 GB20150014666 申请日期 2015.08.18
申请人 INTEL CORPORATION 发明人
分类号 主分类号
代理机构 代理人
主权项
地址