发明名称 整列回路及び受信装置
摘要 A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal.
申请公布号 JP5788308(B2) 申请公布日期 2015.09.30
申请号 JP20110281916 申请日期 2011.12.22
申请人 ルネサスエレクトロニクス株式会社 发明人 野崎 暁弘
分类号 H04L12/953;H04L13/08 主分类号 H04L12/953
代理机构 代理人
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