| 摘要 |
<p>The invention relates to a data processing apparatus (12) for the reception of LDPC encoded signals. At the transmitter, after encoding information bits with an LDPC code prescribed in the DVB-S.2 specification and having a code length of 64,800 and an encoding rate of 2/3 (21), there is a demultiplexer (25) allocating mb code bits to mb symbol bits. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8 × 2 code bits and 8 × 2 symbol bits of two successive 256QAM symbols are represented by b i and y i , respectively, the multiplexer is allocating b 0 to y 15 , b 1 to y 7 , b 2 to y 1 , b 3 to y 5 , b 4 to y 6 , b 5 to y 13 , b 6 to y 11 , b 7 to y 9 , b 8 to y 8 , b 9 to y 14 , b 10 to y 12 , b 11 to y 3 , b 12 to y 0 , b 13 to y 10 , b 14 to y 4 and b 15 to y 2 . The reception apparatus (12) comprises the corresponding multiplexer (54) and an LDPC decoding section (56). The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.</p> |
