Semiconductor device and method for forming a semiconductor device

摘要

A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a first configuration region of emitter-side insulated gate bipolar transistor structures and a second configuration region of emitter-side insulated gate bipolar transistor structures. The first configuration region and the second configuration region are arranged at a main surface of a semiconductor substrate of the semiconductor device. Further, the IGBT arrangement includes a collector layer and a drift layer. The collector layer is arranged at a backside surface of the semiconductor substrate and the drift layer is arranged between the collector layer and the emitter-side IGBT structures of the first configuration region and the second configuration region. Additionally, the collector layer includes at least a first doping region laterally adjacent to a second doping region. The first doping region and second doping region include different charge carrier life times, different conductivity types or different doping concentrations.

主权项

1. A semiconductor device comprising an insulated gate bipolar transistor arrangement,
the insulated gate bipolar transistor arrangement comprising at least a first configuration region of emitter-side insulated gate bipolar transistor structures and a second configuration region of emitter-side insulated gate bipolar transistor structures, wherein the first configuration region and the second configuration region are arranged at a main surface of a semiconductor substrate of the semiconductor device, wherein the insulated gate bipolar transistor arrangement comprises a collector layer and a drift layer which are part of the semiconductor substrate, wherein the collector layer is arranged at a backside surface of the semiconductor substrate of the semiconductor device and the drift layer is arranged between the collector layer and the emitter-side insulated gate bipolar transistor structures of the first configuration region and the second configuration region, wherein the collector layer comprises at least a first doping region laterally adjacent to a second doping region, wherein the first doping region and the second doping region comprise different charge carrier life times, different conductivity types or different doping concentrations, wherein the first configuration region is located with at least a partial lateral overlap to the first doping region and the second configuration region is located with at least a partial lateral overlap to the second doping region, wherein the first configuration region, the first doping region, the second configuration region and the second doping region are configured so that a first average density of free charge carriers within a part of the drift layer facing the first doping region differs from a second average density of free charge carriers within a part of the drift layer facing the second doping region by less than 20% of the second average density of free charge carriers in an on-state of the semiconductor device.