发明名称 Integrated circuit fabrication
摘要 A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.
申请公布号 US9147608(B2) 申请公布日期 2015.09.29
申请号 US201414486890 申请日期 2014.09.15
申请人 MICRON TECHNOLOGY, INC. 发明人 Tran Luan C.;Lee John;Liu Zengtao;Freeman Eric;Nielsen Russell
分类号 H01L21/8242;H01L21/768;H01L21/033;H01L21/311;H01L23/544;H01L27/105;H01L21/306;H01L21/308 主分类号 H01L21/8242
代理机构 Knobbe, Martens, Olson & Bear LLP 代理人 Knobbe, Martens, Olson & Bear LLP
主权项 1. A method for integrated circuit fabrication, comprising: forming a plurality of mask lines in a first region of an integrated circuit structure, wherein the mask lines form loops, each loop having looped ends at ends of the loop; depositing a selectively definable material over the integrated circuit structure; patterning the selectively definable material to expose portions of the mask lines between the loop ends, while covering a width of the mask lines at the loop ends, and while defining a plurality of features in a second region of the integrated circuit structure, wherein the patterned selectively definable material and the exposed portions of the mask lines form a mask; and transferring a pattern defined by the mask to underlying material, wherein a minimum width of the features in the second region is greater than a minimum width of the mask lines.
地址 Boise ID US