发明名称 Method of forming via hole
摘要 The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned layer is formed on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer. The patterned layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.
申请公布号 US9147601(B2) 申请公布日期 2015.09.29
申请号 US201414541148 申请日期 2014.11.14
申请人 UNITED MICROELECTRONICS CORP. 发明人 Wu Cheng-Han;Yu Chun-Chi
分类号 H01L21/311;H01L21/302;H01L21/768;H01L21/3213;H01L21/033;H01L21/027 主分类号 H01L21/311
代理机构 代理人 Hsu Winston;Margo Scott
主权项 1. A method of forming via hole, comprising: providing a substrate, wherein at least a first region is defined on the substrate; forming a dielectric layer and a blocking layer on the substrate, wherein the blocking layer is disposed on the dielectric layer; removing a portion of the blocking layer in the first region; forming a patterned layer on the blocking layer such that a sidewall of the blocking layer is completely covered by the patterned layer, wherein the patterned layer comprises a plurality of holes arranged in a regular array wherein the area of the hole array is greater than that of the first region, and the dielectric layer is exposed by the holes; and patterning the dielectric layer by using the patterned layer as a mask to form at least a via hole in the dielectric layer in the first region.
地址 Science-Based Industrial Park, Hsin-Chu TW