Phase locking for multiple serial interfaces

摘要

An arrangement is described which reduces the number of phase locked loops (PLLs) required in a typical high speed serial interface system. A reference clock is sent from a transmitter on a main board to a receiver on a system board, which employs a PLL that also drives a transmitter on the system board. The transmitter on the system board transmits a data signal to a receiver on the main board which does not require a PLL. Rather, the receiver on the main board is clocked with a static-phase, master reference clock, and the phase of the reference clock sent from the main board is controlled so as to achieve synchronism of the data signal received by the main board receiver using the static-phase, master reference clock. In this way, each high speed serial interface loop between the main board and the individual system boards is controllably adjusted in phase, compensating for interconnection path lengths and providing synchronism between the received signal and the common, static-phase, master reference clock which supplies all the main controller board receivers.

主权项

1. An apparatus comprising:
a bidirectional low-voltage differential signaling (LVDS) interface coupled between first and second terminals each having a receiver and a transmitter for data communication; a phase locked loop coupled to said second receiver and to said second transmitter at said second terminal; a sync word generator forming a sync word for transmission by said second transmitter; a reference clock coupled to said first receiver at said first terminal; and a phase selector for selecting a phase of a signal derived from said reference clock, said selected phase signal being coupled to said first transmitter and communicated to said phase locked loop for synchronizing said second receiver and said second transmitter, said phase selector being controlled responsive to said sync word received by said first receiver from said second transmitter.