Display timing control circuit with adjustable clock divisor and method thereof

摘要

A display timing control circuit is capable of rapidly adjusting display timing to achieve frame synchronization. The display timing control circuit includes an output pixel clock generator, a display timing generator, and a clock adjusting unit. The output pixel clock generator generates an output pixel clock signal according to a reference clock signal and a clock divisor. The display timing generator generates a display timing signal and an output vertical reference signal having an output frame rate according to the output pixel clock signal. The clock adjusting unit adjusts the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal having an input frame rate.

主权项

1. A display timing control circuit, comprising:
an output pixel clock generator, for generating an output pixel clock signal according to a reference clock signal and a clock divisor; a display timing generator, coupled to the output pixel clock generator, for generating a display timing signal and an output vertical reference signal according to the output pixel clock signal, with the output vertical reference signal having an output frame rate; and a clock adjusting unit, coupled to the output pixel clock generator and the display timing generator, for adjusting the clock divisor according to the output pixel clock signal, the output vertical reference signal, and an input vertical reference signal which has an input frame rate, wherein the clock adjusting unit comprises: a frequency shift detector, for detecting a frequency shift between the output vertical reference signal and the input vertical reference signal; a clock divisor generator, coupled to the frequency shift detector, for generating an updated value of the clock divisor according to the frequency shift; and a phase difference detector, coupled to the clock divisor generator, for detecting a phase difference between the output vertical reference signal and the input vertical reference signal, wherein the clock divisor generator determines a divisor adjustment amount of the clock divisor according to the phase difference.