发明名称 Method and system of change evaluation of an electronic design for verification confirmation
摘要 A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.
申请公布号 US9147026(B2) 申请公布日期 2015.09.29
申请号 US201414559583 申请日期 2014.12.03
申请人 Zipalog, Inc. 发明人 Krasnicki Michael;Deng Yue
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Howison & Arnott LLP 代理人 Howison & Arnott LLP
主权项 1. A computer implemented method of change evaluation of an electronic design file for design verification confirmation prior to fabrication of an electronic circuit defined by the electronic design file, comprising the steps of: receiving, at a processor, said electronic design file defining the electronic circuit comprised at least in part of a hierarchy of the electronic circuit having at least one subcomponent of the electronic circuit, wherein the electronic design file defines a functional level electronic design of the electronic circuit; employing, at the processor, a banked signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file; receiving, at the processor, at least one review request of said at least one subcomponent of the electronic circuit defined by the electronic design file; generating, at the processor, a current signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file in response to said at least one review request; determining, at the processor, a difference based at least in part upon said current signature associated with the electronic design file and said banked signature associated with the electronic design file; and evaluating, at the processor, an equivalence of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one reviewed subcomponent of the electronic circuit defined by the electronic design file.
地址 Plano TX US