Half-rate clock and data recovery circuit

摘要

A half-rate clock and data recovery (CDR) circuit includes a first and a second gated voltage-controlled oscillators (GVCOs) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock. A loop filter converts either the first output current or the second output current to a first control voltage to control the second clock, and generates a second control voltage according to the first control voltage to control the first clock. A lock detector receives the reference signal and the second divided clock, and accordingly generates a lock signal.

主权项

1. A half-rate clock and data recovery (CDR) circuit,
comprising: a first gated voltage-controlled oscillator configured to generate a first clock oscillating at about half a frequency of an input data; a second gated voltage-controlled oscillator configured to generate a second clock oscillating at about half the frequency of the input data; a first frequency detector coupled to receive a reference signal and a second divided clock derived from the second clock, and configured to generate a first output current according to the reference signal and the second divided clock, the first frequency detector being turned off in data recovery mode to reduce power consumption; a second frequency detector coupled to receive the second divided clock and a first divided clock derived from the first clock, and configured to generate a second output current according to the first divided clock and the second divided clock, the second frequency detector being turned off in frequency presetting mode to reduce power consumption; a loop filter configured to convert either the first output current or the second output current to a first control voltage that is then fed to the second gated voltage-controlled oscillator to control an oscillation frequency of the second clock, and the loop filter configured to generate a second control voltage according to the first control voltage, the second control voltage then being fed to the first gated voltage-controlled oscillator to control an oscillation frequency of the first clock; and a lock detector coupled to receive the reference signal and the second divided clock, and configured to accordingly generate a lock signal.