发明名称 | Recessed and embedded die coreless package | ||
摘要 | Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands. | ||
申请公布号 | US9147669(B2) | 申请公布日期 | 2015.09.29 |
申请号 | US201414254474 | 申请日期 | 2014.04.16 |
申请人 | Intel Corporation | 发明人 | Guzek John |
分类号 | H01L23/02;H01L23/00;H01L21/683;H01L23/498;H01L23/538;H01L25/10;H01L25/16 | 主分类号 | H01L23/02 |
代理机构 | Winkle, PLLC | 代理人 | Winkle, PLLC |
主权项 | 1. A method comprising; forming a cavity in a plating material; attaching a die in the cavity; forming a dielectric material adjacent the die and over the plating material; forming vias through the dielectric material in a region of the dielectric material adjacent the die; forming package-on-package land areas in the plating material by removing a portion of the plating material within the vias; forming package-on-package land structures in the package-on-package land areas; forming vias through the dielectric material in the die area to expose die pads on the die; forming die pad interconnect structures in the die area vias and forming package-on-package interconnect structures in the dielectric region vias; and removing the plating material to expose the die and the package-on-package land structures. | ||
地址 | Santa Clara CA US |