Adding predefined offset to coarse ADC residue output to SAR

摘要

A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

主权项

1. A successive approximation register analog to digital converter (SAR ADC), configured to receive an input voltage and a set of reference voltages, comprising:
a charge sharing DAC comprising an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors; a zero crossing detector coupled to the charge sharing DAC, the zero crossing detector configured to generate a digital output; a coarse ADC (analog to digital converter) configured to receive the input voltage and configured to generate a coarse output, wherein a predefined offset is added to a residue of the coarse ADC; and a successive approximation register (SAR) state machine, coupled to the coarse ADC and the zero crossing detector and, configured to generate a plurality of control signals, wherein the plurality of control signals is configured to operate the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.