Handheld imaging device with multi-core image processor integrating common bus interface and dedicated image sensor interface

摘要

A handheld imaging device includes an image sensor for sensing an image; a multi-core processor for processing the sensed image; and a program memory provided external to the multi-core processor, and communicating therewith via a communication bus. The multi-core processor includes a bus interface for interfacing with the communication bus, and further includes an image sensor interface for interfacing with the image sensor separately from the communication bus and the bus interface. The multi-core processor includes a plurality of parallel processing units connected by a crossbar switch to form the multi-core.

主权项

1. A device, comprising:
an image sensor for sensing an image; and a processor disposed on a single wafer substrate, the processor comprising:
an image sensor interface connected to the image sensor and configured to receive data associated with the sensed image and provide control information to the image sensor;a multi-core processor for processing the data associated with the sensed image, wherein the multi-core processor includes a plurality of interconnected parallel processing units;a program memory provided external to the multi-core processor, and communicating therewith via a communication bus;a bus interface connected to the multi-core processor and interfacing with the communication bus, wherein the multi-core processor interfaces with the image sensor interface separately from the communication bus and the bus interface;a data interface for receiving data and decoding the data into an image processing script;a central processor for executing an image processing language interpreter on the image processing script, and providing instructions to the multi-core processor to process the sensed image in accordance with the image processing script; anda data cache connected to the plurality of interconnected parallel processing units via a plurality of buses,wherein the plurality of buses are arranged in parallel between the data cache and each of the plurality of interconnected processing units.