Process for fabricating a transistor comprising nanoscale semiconductor features using block copolymers

摘要

A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.

主权项

1. A process for fabricating at least one transistor comprising an active semiconductor region on or in a substrate, said active semiconductor region comprising a source region, a drain region, and a channel region covered with a gate, the process comprising:
producing a primary etching mask on a surface of said active semiconductor region, said primary etching mask containing at least one primary aperture of dimensions Lx and Ly in a XY plane parallel to a plane of said active semiconductor region, wherein the XY plane is defined by a first direction X and a second direction Y; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains, said first and second polymer domains having dimensions Lx and LyA and Lx and LyB, respectively, the dimensions LyA and LyB being nanoscale dimensions; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures distributed in the second direction Y; etching said active semiconductor region through said secondary apertures in order to define nanoscale self-aligned semiconductor features of dimensions Lx and LyA or Lx and LyB in the channel region in the second direction Y, said nanoscale self-aligned semiconductor features being distributed along the second direction Y; and producing said gate on a surface of said nanoscale self-aligned semiconductor features, wherein the transistor is configured to flow a current between the source region and the drain region in the first direction X.