发明名称 Memory process
摘要 A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer.
申请公布号 US9147604(B2) 申请公布日期 2015.09.29
申请号 US201414582899 申请日期 2014.12.24
申请人 NANYA TECHNOLOGY CORPORATION 发明人 Gopalan Vivek;Kerr Robert;Tsai Hung-Ming
分类号 H01L27/108;H01L21/768 主分类号 H01L27/108
代理机构 J.C. Patents 代理人 J.C. Patents
主权项 1. A memory process, comprising: providing a substrate, wherein the substrate has therein a plurality of trenches and a plurality of conductive lines buried in the trenches and has thereon an array area, and each of the conductive lines has an array portion in the array area; defining a contact area apart from the array area on the substrate, wherein each of the conductive lines has a contact portion in the contact area; etching the substrate between the contact portions of the conductive lines down to below tops of the conductive layers to form a plurality of gaps between the contact portions of the conductive lines; and filling the gaps with an insulating layer.
地址 Taoyuan TW