Computer system including reconfigurable arithmetic device with network of processor elements

摘要

A computer system that includes a central processing unit, a random-access-memory interface, a random-access memory whose addresses are allocated in an address space of the random-access-memory interface, and a reconfigurable arithmetic device is described herein. The reconfigurable arithmetic device includes input terminals, output terminals, a network of plurality of processor elements, a built-in random-access memory, a control unit, an inter-processor-element network and a configuration-data memory. In accordance with configuration on data from the configuration-data memory, the inter processor-element network is capable of changing the connection state of the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, and the arithmetic function of the reconfigurable arithmetic device is capable of being dynamically changed.

主权项

1. A reconfigurable arithmetic device, comprising:
a plurality of processor elements configured to perform first arithmetic processes corresponding to a first type of instruction and second arithmetic processes corresponding to a second type of instruction; an inter-processor-element network configured to change a connection state of the processor elements; a random-access memory (RAM); and a control unit,
wherein the first type of instruction is written into the RAM at a first address, data for the first type of instruction is written into the RAM at a second address, and data for the second type of instruction is written into the RAM at a fixed input address other than the first and second addresses,wherein when the first type of instruction is written at the first address, the control unit decodes the first type of instruction and sets the processor elements to a state to perform the first arithmetic processes, andwherein, when data for the second type of instruction is written at the fixed input address, the control unit sets the processor elements to a state to perform the second arithmetic processes.