发明名称 Method and apparatus for repairing high capacity/high bandwidth memory devices
摘要 Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.
申请公布号 US9146811(B2) 申请公布日期 2015.09.29
申请号 US201414305985 申请日期 2014.06.16
申请人 Micron Technology, Inc. 发明人 LaBerge Paul A.;Jeddeloh Joseph M.
分类号 G06F7/02;H03M13/00;G06F11/10;G11C29/00;G06F11/08;H03M13/09 主分类号 G06F7/02
代理机构 Dorsey & Whitney LLP 代理人 Dorsey & Whitney LLP
主权项 1. An apparatus, comprising: a plurality of memories coupled to each other via a plurality of conductors; a logic die coupled to the plurality of memories and configured to read data from the plurality of memories, the logic die including an error checking system configured to generate an error checking code corresponding to data read from an address in a memory of the plurality of memories, the error checking system fluffier configured to indicate an error if a stored error checking code corresponding to the data read from the address does not match the generated error checking code; and a state machine configured to determine whether the error originated in the memory of the plurality of memories or in a conductor of the plurality of conductors, wherein the state machine, responsive to a determination that the error originated in a conductor of the plurality of conductors, is configured to determine whether a fault of the plurality of conductors is related to coupling addresses to the plurality of memories or related to coupling data to and from the plurality of memories.
地址 Boise ID US