| 发明名称 |
System architecture with multiple memory types, including programmable impedance memory elements |
| 摘要 |
A system can include a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path. |
| 申请公布号 |
US9147464(B1) |
申请公布日期 |
2015.09.29 |
| 申请号 |
US201313846539 |
申请日期 |
2013.03.18 |
| 申请人 |
Adesto Technologies Corporation |
发明人 |
McKernan Ed;Wing Malcolm;Sunkavalli Ravi |
| 分类号 |
G11C11/24;G11C11/409;G11C13/00 |
主分类号 |
G11C11/24 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A system, comprising:
a first memory section comprising a plurality of volatile memory cells accessible via a first data path having a first bit width; a second memory section comprising a plurality of programmable impedance memory cells, each having at least one solid electrolyte layer; and a second data path configured to transfer data between the first and second memory sections independent of the first data path, the second data path having a greater bit width than the first data path; and a transfer circuit comprising a data copy engine configured to automatically transfer a block of data from the first memory section to the second memory section in response to a save command. |
| 地址 |
Sunnyvale CA US |
