发明名称 Method and apparatus for performing fast incremental resynthesis
摘要 A method for designing a system on a target device is disclosed. A first netlist with a first set of functionally invariant boundaries (FIBs) is generated after performing extraction during synthesis of a first version of the system in a first compilation. One or more of the FIBs is invalidated from the first set after performing optimizations during synthesis in the first compilation resulting in a second netlist with a second set of FIBs. A third netlist with a third set of FIBs is generated after performing extraction during synthesis of a second version of the system having a changed portion in a second compilation. Connectivity of matching nodes from the first netlist and the third netlist reaching FIBs is traversed to identify equivalent nodes associated with identical regions. The identical region in the third netlist is replaced with an optimized synthesized region from the second netlist.
申请公布号 US9147023(B1) 申请公布日期 2015.09.29
申请号 US201414228378 申请日期 2014.03.28
申请人 Altera Corporation 发明人 Chen Doris Tzu Lang;Singh Deshanand
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人 Cho L.
主权项 1. A method for designing a system on a target device, comprising: generating a first netlist with a first set of functionally invariant boundaries (FIBs) for a first version of the system in a first compilation; invalidating one or more of the FIBs from the first set after performing optimizations during synthesis resulting in a second netlist with a second set of FIBs; generating a third netlist with a third set of FIBs of a second version of the system having a changed portion in a second compilation; and replacing a region in the third netlist with an optimized synthesized region from the second netlist identified as being identical, wherein at least one of the generating, invalidating, and replacing is performed by a processor.
地址 San Jose CA US