Controlled-precision iterative arithmetic logic unit

摘要

A controlled-precision Iterative Arithmetic Logic Unit (IALU) included in a processor produces sub-precision results, i.e. results having a bit precision less than full precision. In one embodiment, the controlled-precision IALU comprises an arithmetic logic circuit and a precision control circuit. The arithmetic logic circuit is configured to iteratively process operands of a first bit precision to obtain a result. The precision control circuit is configured to end the iterative operand processing when the result achieves a programmed second bit precision less than the first bit precision. In one embodiment, the precision control circuit causes the arithmetic logic circuit to end the iterative operand processing in response to an indicator received by the control circuit. The controlled-precision IALU further comprises rounding logic configured to round the sub-precision result.

主权项

1. A method of performing an iterative arithmetic operation in a processor, comprising:
iteratively processing operands of a first bit precision to obtain a result; ending the iterative processing when the result achieves a programmed second bit precision less than the first bit precision: and rounding the result; wherein rounding the result comprises:
aligning a rounding value with a least significant bit (LSB) of the result; andconditionally adding the aligned rounding value to the result; wherein aligning the rounding value with the LSB of the result comprises:
shifting the rounding value so that the rounding value has a logic one located at a bit position corresponding to the LSB of the result.