发明名称 Performance of accesses from multiple processors to a same memory location
摘要 A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value. The processor is configured in response to the predefined request to perform the operation on data within the storage location allocated to the data item.
申请公布号 US9146870(B2) 申请公布日期 2015.09.29
申请号 US201313949434 申请日期 2013.07.24
申请人 ARM Limited 发明人 Francis Hedley James;Elliott Robert Martin;Devereux Ian Victor;Croxford Daren
分类号 G06F13/38;G06F12/08;G06F12/12;G06F9/52;G06F3/03 主分类号 G06F13/38
代理机构 Nixon & Vanderhye P.C. 代理人 Nixon & Vanderhye P.C.
主权项 1. A processing apparatus comprising: a plurality of processors for processing data; a hierarchical memory system comprising a plurality of data stores for storing said data, said hierarchical memory system comprising a memory accessible to all of said plurality of processors, and a plurality of caches corresponding to each of said plurality of processors, each of said caches being accessible to said corresponding processor and comprising a plurality of storage locations and a corresponding plurality of indicators, said memory having a lower hierarchy than said plurality of caches; cache coherency control circuitry for maintaining coherency of data stored in said hierarchical memory system; each of said plurality of processors being configured to respond to receipt of a predefined request to perform an operation on a data item, to determine if said cache corresponding to said processor receiving said request comprises a storage location allocated to said data item; and if not, said processing apparatus is configured to: allocate a storage location within said cache to said data item,set said indicator corresponding to said storage location to indicate that said storage location is storing a delta value,set data in said allocated storage location to an initial value, and said processor is configured in response to said predefined request to perform said operation on data within said storage location allocated to said data item.
地址 Cambridge GB