Programmable physical address mapping for memory

摘要

A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.

主权项

1. A memory comprising:
a set of memory cells arranged as a plurality of rows and one or more banks; address decode logic having programmable physical address mapping, the address decode logic to select a bank and a row of the selected bank for a memory access based on the programmable physical address mapping and a physical address associated with the memory access, the address decode logic comprising:
a plurality of mapping tables, each mapping table representing a corresponding physical address mapping of a plurality of physical address mappings including the programmable physical address mapping;a programmable storage element to store an indicator of a selected mapping table of the plurality of mapping tables; andlogic coupled to the programmable storage element and having access to the selected mapping table, the logic to perform a lookup into the selected mapping table to determine which bank is to be accessed for the memory access and to determine a bank offset identifying a row of the bank to be accessed for the memory access, wherein the logic is to perform the lookup using the physical address associated with the memory access; and access analysis logic to determine an access pattern of memory accesses to the memory, to select a physical address mapping based on the access pattern, and to program the address decode logic to implement the selected physical address mapping, wherein the access analysis logic is to select a column-major address mapping as the physical address mapping responsive to the access pattern identifying a stride patterns greater than one and to select a row-major address mapping as the physical address mapping responsive to the access pattern identifying a stride, pattern equal to one.