Branch prediction preloading

摘要

Embodiments relate to branch prediction preloading. An aspect includes a system for branch prediction preloading. The system includes an instruction cache and branch target buffer (BTB) coupled to a processing circuit, the processing circuit configured to perform a method. The method includes fetching a plurality of instructions in an instruction stream from the instruction cache, and decoding a branch prediction preload instruction in the instruction stream. An address of a predicted branch instruction is determined based on the branch prediction preload instruction. A predicted target address is determined based on the branch prediction preload instruction. A mask field is identified in the branch prediction preload instruction, and a branch instruction length is determined based on the mask field. Based on executing the branch prediction preload instruction, the BTB is preloaded with the address of the predicted branch instruction, the branch instruction length, the branch type, and the predicted target address.

主权项

1. A system for branch prediction preloading, the system comprising:
an instruction cache; a branch target buffer; and a processing circuit coupled to the instruction cache and the branch target buffer, the processing circuit configured to perform a method comprising:
fetching a plurality of instructions in an instruction stream from the instruction cache;decoding a branch prediction preload instruction in the instruction stream;determining, by the processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction;determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction;identifying a mask field in the branch prediction preload instruction;determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field; andbased on executing the branch prediction preload instruction, preloading the branch target buffer with the address of the predicted branch instruction, the branch instruction length, and the predicted target address associated with the predicted branch instruction.