发明名称 High resolution capacitance to code converter
摘要 An integration circuit including a first capacitor is operatively coupled to a comparator. The comparator is configured to compare a first capacitor voltage of the first capacitor to a reference voltage and produce a first comparator output based on the comparison. A current generator is operatively coupled with the integration circuit and configured to balance charge on the first capacitor. A control unit is operatively coupled to the comparator and the current generator and configured to balance charge on the first capacitor by sensing the first comparator output and controlling the current generator based on the first comparator output.
申请公布号 US9146650(B2) 申请公布日期 2015.09.29
申请号 US201414475034 申请日期 2014.09.02
申请人 PARADE TECHNOLOGIES, LTD. 发明人 Ogirko Roman;Klein Hans;Maharyta Andriy
分类号 G09G5/00;G06F3/041;G06F3/044;G06F7/38 主分类号 G09G5/00
代理机构 Morgan, Lewis & Bockius LLP 代理人 Morgan, Lewis & Bockius LLP
主权项 1. A method comprising: coupling a first capacitor to an electrode of a capacitive sense array; integrating charge received from the electrode of the capacitance sense array with the first capacitor; decoupling the first capacitor from the electrode of the capacitive sense array; coupling a second capacitor to the electrode of the capacitive sense array; concurrently integrating charge received from the electrode of the capacitive sense array with the second capacitor and supplying a first balancing charge to the first capacitor; ceasing to supply the first balancing charge to the first capacitor when the charge on the first capacitor falls below a predetermined level; and calculating a first value representative of a capacitance of the electrode of the capacitive sense array based on a measure of the first balancing charge supplied to the first capacitor.
地址 Santa Clara CA US