IC and test interposer with stimulus generator circuitry and TAP

摘要

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

主权项

1. An electrical device comprising;
(A) an integrated circuit die having functional circuitry and test circuitry, the die having through silicon input vias and through silicon output vias coupled to the functional circuitry and the test circuitry, the integrated circuit die having a first face and the through silicon vias having contact points on the first face; and (B) a test interposer having a first face and a second face, the test interposer having through silicon input vias and through silicon output vias with contact points on the first and second faces, the contact points on the first face of the interposer being coupled with contact points on the first face of the integrated circuit die, the test interposer including: (1) a first multiplexer having a first input coupled with the through silicon input vias of the test interposer, a second input, a control input, and an output coupled with the through silicon input vias of the integrated circuit die; (2) a second multiplexer having a first input coupled with the through silicon input vias of the test interposer, a second input, a control input, and an output coupled with the through silicon input vias of the integrated circuit die; (3) stimulus generator circuitry having a control input and an output coupled with the second input of the first multiplexer; and (4) test access port circuitry having a test data input, a test clock input, a test mode select input, and a test data output, the test access port circuitry having control leads coupled to the first multiplexer, the second multiplexer, and the stimulus generator.