Dual comparator-based error correction scheme for analog-to-digital converters

摘要

An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.

主权项

1. A method comprising:
sampling a first output voltage of a first comparator and a second output voltage of a second comparator during a same binary algorithmic iteration of an analog-to-digital converter (ADC); identifying a first polarity of the first output voltage and a second polarity of the second output voltage; and if the first polarity is equal to the second polarity, inserting at least one redundant capacitor for a next binary algorithmic iteration of the ADC.