| 发明名称 |
Selecting A Low Power State Based On Cache Flush Latency Determination |
| 摘要 |
In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed. |
| 申请公布号 |
US2015268711(A1) |
申请公布日期 |
2015.09.24 |
| 申请号 |
US201414221696 |
申请日期 |
2014.03.21 |
| 申请人 |
Ramani Sundar;Raman Arvind;Mandhani Arvind;Choubal Ashish V.;Muthukumar Kalyan;Durg Ajaya V.;Chakki Samudyatha |
发明人 |
Ramani Sundar;Raman Arvind;Mandhani Arvind;Choubal Ashish V.;Muthukumar Kalyan;Durg Ajaya V.;Chakki Samudyatha |
| 分类号 |
G06F1/32;G06F12/08 |
主分类号 |
G06F1/32 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
a plurality of cores to independently execute instructions; a shared cache coupled to the plurality of cores, the shared cache including a plurality of lines to store data; and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. |
| 地址 |
Bangalore IN |
