PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY

摘要

Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

主权项

1. A method of forming a nanowire transistor on a substrate, the method comprising:
forming a guide opening in a mask layer disposed over a source/drain semiconductor layer of the transistor; depositing a directed self-assembly (DSA) material into the guide opening; segregating the DSA material into an interior polymer region completely surrounded by an exterior polymer region within the guide opening, the interior polymer region having a cylindrical geometry having a diameter; defining a semiconductor channel region of the transistor within the guide opening by removing one of the interior and exterior polymer regions selectively to the other, wherein the semiconductor channel region has a diameter defined by the diameter of the cylindrical geometry of the interior polymer region; removing the other of the interior and exterior polymer regions; depositing a gate dielectric over the semiconductor channel region; and surrounding the semiconductor channel region with an annular gate electrode having an outer diameter self-aligned to the guide opening.