发明名称 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME
摘要 A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V.
申请公布号 US2015270270(A1) 申请公布日期 2015.09.24
申请号 US201514659714 申请日期 2015.03.17
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 KATO Kiyoshi
分类号 H01L27/108;H01L29/786 主分类号 H01L27/108
代理机构 代理人
主权项 1. A semiconductor memory device comprising: a memory cell comprising: a first transistor, a gate of the first transistor being electrically connected to a first wiring, one of a source and a drain of the first transistor being electrically connected to a fourth wiring, and the other of the source and the drain of the first transistor being electrically connected to a node;a second transistor, a gate of the second transistor being electrically connected to the node, and one of a source and a drain of the second transistor being electrically connected to a third wiring; anda capacitor, one electrode of the capacitor being electrically connected to the node, and the other electrode of the capacitor being electrically connected to a second wiring, wherein a channel formation region of the first transistor comprises an oxide semiconductor layer, wherein each of a channel length and a channel width of the first transistor is shorter than 100 nm, wherein a maximum potential of the first wiring is lower than or equal to 2 V, and wherein electrostatic capacitance of the capacitor is greater than or equal to 5×10−12 F and less than or equal to 200×10−12 F.
地址 Atsugi-shi JP