主权项 |
1. A semiconductor memory device comprising:
a memory cell comprising:
a first transistor, a gate of the first transistor being electrically connected to a first wiring, one of a source and a drain of the first transistor being electrically connected to a fourth wiring, and the other of the source and the drain of the first transistor being electrically connected to a node;a second transistor, a gate of the second transistor being electrically connected to the node, and one of a source and a drain of the second transistor being electrically connected to a third wiring; anda capacitor, one electrode of the capacitor being electrically connected to the node, and the other electrode of the capacitor being electrically connected to a second wiring, wherein a channel formation region of the first transistor comprises an oxide semiconductor layer, wherein each of a channel length and a channel width of the first transistor is shorter than 100 nm, wherein a maximum potential of the first wiring is lower than or equal to 2 V, and wherein electrostatic capacitance of the capacitor is greater than or equal to 5×10−12 F and less than or equal to 200×10−12 F. |