| 摘要 |
A vertical FET, including a source layer, a channel layer, a drain layer and a gate dielectric, the source layer being coupled with a source electrode, the channel layer being deposited on top of the source layer, the drain layer being deposited on top of the channel layer and being coupled with a drain electrode, the gate dielectric being conformally deposited within a cylindrical niche through the drain layer down to the channel layer, the gate dielectric being encircled by the drain layer, the gate dielectric being coupled with a gate electrode deposited within the cylindrical niche, when a threshold voltage Is applied to the gate electrode a channel is formed between the source layer and the drain layer, a length of the channel corresponding to a thickness of the channel layer and a width of the channel corresponding to a perimeter of the cylindrical niche. |
